Invention Grant
- Patent Title: Method of forming an interconnect structure on an integrated circuit die
- Patent Title (中): 在集成电路管芯上形成互连结构的方法
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Application No.: US11720748Application Date: 2005-11-24
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Publication No.: US07867889B2Publication Date: 2011-01-11
- Inventor: Wim Besling
- Applicant: Wim Besling
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Priority: EP04300831 20041201
- International Application: PCT/IB2005/053892 WO 20051124
- International Announcement: WO2006/059261 WO 20060608
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A method of forming an interconnect structure, comprising forming a first interconnect layer (123) embedded in a first dielectric layer (118), forming a dielectric tantalum nitride barrier (150) by means of atomic layer deposition on the surface of the first interconnect (123), depositing a second dielectric layer (134) over the first interconnect (123) and the barrier (150) and etching a via (154) in the dielectric layer (134) to the barrier (150). The barrier (150) is then exposed to a treatment through the via (154) to change it from the dielectric phase to the conductive phase (180) and the via (154) is subsequently filled with conductive material (123).
Public/Granted literature
- US20100013098A1 METHOD OF FORMING AN INTERCONNECT STRUCTURE ON AN INTEGRATED CIRCUIT DIE Public/Granted day:2010-01-21
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