Invention Grant
- Patent Title: Semiconductor integrated circuit with solder bump
- Patent Title (中): 半导体集成电路与焊锡凸块
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Application No.: US12034997Application Date: 2008-02-21
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Publication No.: US07868409B2Publication Date: 2011-01-11
- Inventor: Takao Sasaki
- Applicant: Takao Sasaki
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Priority: JP2007-041515 20070221
- Main IPC: H01L23/58
- IPC: H01L23/58
Abstract:
A semiconductor integrated circuit which is connected to a substrate by solder bumps wherein, when at least one solder bump is connected to a signal line of the semiconductor integrated circuit and the semiconductor integrated circuit is mounted on the substrate, the semiconductor integrated circuit is bonded to the substrate by the solder bump, and the interconnection to the substrate is made by dummy bumps forming wires at the substrate side.
Public/Granted literature
- US20080290475A1 SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2008-11-27
Information query
IPC分类:
