Invention Grant
- Patent Title: MOS device with a high voltage isolation structure
- Patent Title (中): MOS器件具有高电压隔离结构
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Application No.: US11280888Application Date: 2005-11-16
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Publication No.: US07868422B2Publication Date: 2011-01-11
- Inventor: Kuo-Ting Lee , You-Kuo Wu , Fu-Hsin Chen , An-Ming Chiang
- Applicant: Kuo-Ting Lee , You-Kuo Wu , Fu-Hsin Chen , An-Ming Chiang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: K&L Gates LLP
- Main IPC: H01L29/06
- IPC: H01L29/06

Abstract:
The present invention discloses a semiconductor structure. A buried layer of a first polarity type is constructed on a semiconductor substrate. A first epitaxial layer of a second polarity type is formed on the buried layer. A second epitaxial layer of the second polarity type is formed on the buried layer. An isolation structure of the first polarity type is formed between the first and second epitaxial layers on the buried layer. A first well of the second polarity type is formed on the first epitaxial layer. A second well of the second polarity type is formed on the second epitaxial layer. A third well of the first polarity type is formed between the first and second wells, on the isolation structure. The isolation structure interfaces with the buried layer and the third well, thereby substantially blocking a leakage current path between the first and the second wells.
Public/Granted literature
- US20070108602A1 MOS device with a high voltage isolation structure Public/Granted day:2007-05-17
Information query
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