An embodiment of an input-buffer circuit may include an input stage with an inverter having an input operable to receive a signal to be translated. The input stage may include a limiting circuit coupled to the input stage for arresting quiescent current. Additional embodiments of an input-buffer circuit formed according to the subject matter disclosed herein may include feedback transistors suited to provide additional current to the input stage and a hysteresis circuit suited to provide hysteresis current to the input stage when an input signal has a high-frequency change rate.