Invention Grant
- Patent Title: Phase-locked loop (PLL) circuit and method
- Patent Title (中): 锁相环(PLL)电路及方法
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Application No.: US11842004Application Date: 2007-08-20
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Publication No.: US07868670B2Publication Date: 2011-01-11
- Inventor: Georg Becke , Gerd Rombach
- Applicant: Georg Becke , Gerd Rombach
- Applicant Address: DE Freising
- Assignee: Texas Instruments Deutschland GmbH
- Current Assignee: Texas Instruments Deutschland GmbH
- Current Assignee Address: DE Freising
- Agent John J. Patti; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Priority: DE102006038869 20060818
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A phase-locked loop (PLL) circuit includes a reference clock divider with a reference clock input, a phase-frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a feedback divider. A method of operating the PLL circuit comprises the steps of detecting a failure of a reference clock applied to the reference clock input, disabling the charge pump upon detection of a reference clock failure, monitoring the reference clock to detect restoration of a regular reference clock, upon detection of a regular reference clock, detecting occurrence of the next pulse from the feedback divider, and enabling the charge pump upon detection of the next pulse from the feedback divider.
Public/Granted literature
- US20080054960A1 PHASE-LOCKED LOOP (PLL) CIRCUIT AND METHOD Public/Granted day:2008-03-06
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