Invention Grant
US07868670B2 Phase-locked loop (PLL) circuit and method 有权
锁相环(PLL)电路及方法

Phase-locked loop (PLL) circuit and method
Abstract:
A phase-locked loop (PLL) circuit includes a reference clock divider with a reference clock input, a phase-frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a feedback divider. A method of operating the PLL circuit comprises the steps of detecting a failure of a reference clock applied to the reference clock input, disabling the charge pump upon detection of a reference clock failure, monitoring the reference clock to detect restoration of a regular reference clock, upon detection of a regular reference clock, detecting occurrence of the next pulse from the feedback divider, and enabling the charge pump upon detection of the next pulse from the feedback divider.
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