Invention Grant
US07869239B2 Layout structure of bit line sense amplifiers for a semiconductor memory device
有权
用于半导体存储器件的位线读出放大器的布局结构
- Patent Title: Layout structure of bit line sense amplifiers for a semiconductor memory device
- Patent Title (中): 用于半导体存储器件的位线读出放大器的布局结构
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Application No.: US12078724Application Date: 2008-04-03
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Publication No.: US07869239B2Publication Date: 2011-01-11
- Inventor: Young-Sun Min , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
- Applicant: Young-Sun Min , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Lee & Morse, P.C.
- Priority: KR10-2007-0033135 20070404
- Main IPC: G11C5/02
- IPC: G11C5/02

Abstract:
A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.
Public/Granted literature
- US20080259668A1 Layout structure of bit line sense amplifiers for a semiconductor memory device Public/Granted day:2008-10-23
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