Invention Grant
- Patent Title: Semiconductor device and semiconductor memory tester
- Patent Title (中): 半导体器件和半导体存储测试仪
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Application No.: US12142278Application Date: 2008-06-19
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Publication No.: US07869240B2Publication Date: 2011-01-11
- Inventor: Yuui Shimizu , Shigeo Ohshima , Mie Matsuo
- Applicant: Yuui Shimizu , Shigeo Ohshima , Mie Matsuo
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JPP2007-161558 20070619
- Main IPC: G11C5/02
- IPC: G11C5/02 ; G11C5/06 ; H01L23/52

Abstract:
A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.
Public/Granted literature
- US20090003103A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY TESTER Public/Granted day:2009-01-01
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