Invention Grant
- Patent Title: Transmission lines for CMOS integrated circuits
- Patent Title (中): CMOS集成电路的传输线
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Application No.: US12431181Application Date: 2009-04-28
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Publication No.: US07869242B2Publication Date: 2011-01-11
- Inventor: Leonard Forbes , Eugene H. Cloud , Kie Y. Ahn
- Applicant: Leonard Forbes , Eugene H. Cloud , Kie Y. Ahn
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G11C5/02
- IPC: G11C5/02

Abstract:
Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.
Public/Granted literature
- US20090207641A1 NOVEL TRANSMISSION LINES FOR CMOS INTEGRATED CIRCUITS Public/Granted day:2009-08-20
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