A memory module with a module board is disclosed, on the front side of which a plurality of first memory devices are arranged in rows. A plurality of second memory devices are arranged in rows on the back side. The first and second memory devices have a single chip each. Further, a first register device for providing first control signals to first rows of first memory devices and to first rows of second memory devices is provided. A second register device serves to provide first control signals to second rows of first memory devices and to second rows of second memory devices.