Invention Grant
US07869268B2 Phase change memory erasable and programmable by a row decoder 有权
相变存储器可由行解码器擦除和编程

Phase change memory erasable and programmable by a row decoder
Abstract:
An integrated circuit includes a non-volatile memory having memory cells each having a memory point and a selection transistor having a control terminal connected to a word line, a row decoder for supplying word line selection signals, and at least one generator for supplying memory cells with an erase or programming voltage or current. Word line drivers are interposed between the row decoder and the word lines, and are arranged for applying to a word line selected by the row decoder control pulses, the profile of which corresponds to a profile of an erase or programming voltage or current pulse. Application is for particularly but not exclusively to phase change memories.
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