Invention Grant
US07869494B2 Equalizer circuitry for mitigating pre-cursor and post-cursor intersymbol interference 有权
均衡器电路,用于减轻前置和后置符号间符号干扰

Equalizer circuitry for mitigating pre-cursor and post-cursor intersymbol interference
Abstract:
One or more embodiments of the invention comprise a continuous-time equalizer (CTE) for reducing both pre-cursor and post-cursor intersymbol interference (ISI) from data received from a communication channel. One such equalizer comprises two independent stages that process the input signal in parallel. One stage subtracts a scaled version of the derivative of the input signal from a scaled version of the input signal to reduce pre-cursor ISI from the input signal. The other stage adds a scaled version of the derivative of the input signal to a scaled version of the input signal to reduce post-cursor ISI from the input signal. The outputs from the two stages are then multiplied to arrive at an output signal in which both pre- and post-cursor ISI is minimized. Because the scalars used in each of the stages are independent, each can be adjusted for greater manipulation of the ISI-reduced signal.
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