Invention Grant
US07869494B2 Equalizer circuitry for mitigating pre-cursor and post-cursor intersymbol interference
有权
均衡器电路,用于减轻前置和后置符号间符号干扰
- Patent Title: Equalizer circuitry for mitigating pre-cursor and post-cursor intersymbol interference
- Patent Title (中): 均衡器电路,用于减轻前置和后置符号间符号干扰
-
Application No.: US11866813Application Date: 2007-10-03
-
Publication No.: US07869494B2Publication Date: 2011-01-11
- Inventor: Timothy M. Hollis
- Applicant: Timothy M. Hollis
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wong, Cabello, Lutsch, Rutherford & Brucculeri, LLP
- Main IPC: H03H7/40
- IPC: H03H7/40

Abstract:
One or more embodiments of the invention comprise a continuous-time equalizer (CTE) for reducing both pre-cursor and post-cursor intersymbol interference (ISI) from data received from a communication channel. One such equalizer comprises two independent stages that process the input signal in parallel. One stage subtracts a scaled version of the derivative of the input signal from a scaled version of the input signal to reduce pre-cursor ISI from the input signal. The other stage adds a scaled version of the derivative of the input signal to a scaled version of the input signal to reduce post-cursor ISI from the input signal. The outputs from the two stages are then multiplied to arrive at an output signal in which both pre- and post-cursor ISI is minimized. Because the scalars used in each of the stages are independent, each can be adjusted for greater manipulation of the ISI-reduced signal.
Public/Granted literature
- US20090092180A1 EQUALIZER CIRCUITRY FOR MITIGATING PRE-CURSOR AND POST-CURSOR INTERSYMBOL INTERFERENCE Public/Granted day:2009-04-09
Information query