Invention Grant
- Patent Title: Calibration circuit
- Patent Title (中): 校准电路
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Application No.: US11841286Application Date: 2007-08-20
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Publication No.: US07869973B2Publication Date: 2011-01-11
- Inventor: Hideyuki Yoko , Hiroki Fujisawa
- Applicant: Hideyuki Yoko , Hiroki Fujisawa
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory Inc.
- Current Assignee: Elpida Memory Inc.
- Current Assignee Address: JP Tokyo
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Priority: JP2006-224578 20060821
- Main IPC: G01R35/00
- IPC: G01R35/00

Abstract:
To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT1 or ACT2 is activated, and a calibration operation is performed for either the first replica buffer or the second replica buffer. When a second calibration command ZQCL is issued, both of the control signals ACT1, ACT2 are activated and the calibration operation is performed for both the first replica buffer and the second replica buffer.
Public/Granted literature
- US20080046212A1 CALIBRATION CIRCUIT Public/Granted day:2008-02-21
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