Invention Grant
US07870331B2 Fully-buffered dual in-line memory module with fault correction
有权
具有故障校正功能的全缓冲双列直插式内存模块
- Patent Title: Fully-buffered dual in-line memory module with fault correction
- Patent Title (中): 具有故障校正功能的全缓冲双列直插式内存模块
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Application No.: US11655603Application Date: 2007-01-19
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Publication No.: US07870331B2Publication Date: 2011-01-11
- Inventor: Sehat Sutardja , Saeed Azimi
- Applicant: Sehat Sutardja , Saeed Azimi
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
A memory system comprises first memory that includes memory cells that are selectively refreshed at a refresh rate. A test module tests operation of the memory cells at the refresh rate and that identifies T of the memory cells that are inoperable when refreshed at the refresh rate, where T is an integer greater than zero. Content addressable memory (CAM) includes D CAM memory cells where D is an integer greater than or equal to one. An adaptive refresh module selectively adjusts a refresh rate of the first memory based on T and D.
Public/Granted literature
- US20070168812A1 Fully-buffered dual in-line memory module with fault correction Public/Granted day:2007-07-19
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