A p− RESURF region is formed as a surface layer in an n− semiconductor layer. Then, trenches, gate insulating films, and a thick insulating film, gate electrodes, and a gate polysilicon interconnection are formed in this order. Subsequently, a p-well region is formed using the gate polysilicon interconnection as a mask. Then n+ source regions are formed. Since the p− RESURF region is formed and the p-well region is formed after forming the gate electrodes and the gate polysilicon interconnection, the severeness of a high-temperature heat history is lowered and the diffusion depth of the p-well region is decreased. The formation of the p− RESURF region and the shallow p-well region makes it possible to reduce the on-resistance while increasing the breakdown voltage, as well as reducing the gate capacitance.