Invention Grant
- Patent Title: Method and structure for relieving transistor performance degradation due to shallow trench isolation induced stress
- Patent Title (中): 由于浅沟槽隔离引起的应力,缓解晶体管性能退化的方法和结构
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Application No.: US12033322Application Date: 2008-02-19
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Publication No.: US07871895B2Publication Date: 2011-01-18
- Inventor: Ramachandra Divakaruni , Wai-Kin Li , Haining S. Yang
- Applicant: Ramachandra Divakaruni , Wai-Kin Li , Haining S. Yang
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Joseph Petrokaitis
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/336

Abstract:
A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate.
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