Invention Grant
US07872332B2 Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
有权
用于堆叠管芯的互连结构，包括贯穿硅通孔的穿透结构以及相关的系统和方法
- Patent Title: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
- Patent Title (中): 用于堆叠管芯的互连结构，包括贯穿硅通孔的穿透结构以及相关的系统和方法
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Application No.: US12209029Application Date: 2008-09-11
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Publication No.: US07872332B2Publication Date: 2011-01-18
- Inventor: Owen R. Fay , Warren M. Farnworth , David R. Hembree
- Applicant: Owen R. Fay , Warren M. Farnworth , David R. Hembree
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L23/52 ; H01L23/48 ; H01L21/768
Abstract:
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.
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