Invention Grant
US07872491B2 Noise filter circuit, dead time circuit, delay circuit, noise filter method, dead time method, delay method, thermal head driver, and electronic instrument
有权
噪声滤波电路，死区电路，延时电路，噪声滤波法，死区时间法，延时法，热敏头驱动器及电子仪器
- Patent Title: Noise filter circuit, dead time circuit, delay circuit, noise filter method, dead time method, delay method, thermal head driver, and electronic instrument
- Patent Title (中): 噪声滤波电路，死区电路，延时电路，噪声滤波法，死区时间法，延时法，热敏头驱动器及电子仪器
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Application No.: US12335184Application Date: 2008-12-15
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Publication No.: US07872491B2Publication Date: 2011-01-18
- Inventor: Saito Tadamori
- Applicant: Saito Tadamori
- Applicant Address: JP Tokyo
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP Tokyo
- Agency: Oliff & Berridge PLC
- Priority: JP2007-323926 20071214
- Main IPC: H03K17/16
- IPC: H03K17/16 ; H03K19/003
Abstract:
A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first inverter circuit and a signal based on a signal output from the second inverter circuit as a set signal and a reset signal. Each of the first inverter circuit and the second inverter circuit includes a first-conductivity-type transistor and a second-conductivity-type transistor, the capability of one of the first-conductivity-type transistor and the second-conductivity-type transistor being lower than the capability of the other of the first-conductivity-type transistor and the second-conductivity-type transistor.
Public/Granted literature
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