In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK1 to both a hit determination circuit and a second clock gate circuit. The second clock gate circuit 110 passes through the first update clocks CLK1 until reception of a hit signal from the hit determination circuit and delivers second update clocks CLK2 to an up/down counter 106. The up/down counter 106 is operated by the second update clocks CLK2. With this structure, the second update clocks used for adjustment steps can be increased in number during the calibration period.