It is disclosed a combinatorial logic circuit comprising a first logic block (B1) coupled to a supply terminal (VDD) via a first resistor means (RI) and via a second resistor means (R2) for receiving respective first and second supply currents (111, 112). The circuit further comprises a second logic block (B2) coupled to the supply terminal (VDD) via the first resistor means (R1) and via the second resistor means (R2) for receiving respective third and fourth supply currents (122, 121). A first output terminal (Q−) coupled to the first block (B1) and to the first resistor means (R1). A second output terminal (Q+) coupled to the second logic block (B2) and to the second resistor means (R2). A first current source (I0) coupled to at least one of the first output terminal (Q−) and/or second output terminal (Q+) for providing a first supply current (I1) through the first resistor means (R1), which is substantially equal to a second supply current (I2) through the second resistor means (R2).