A duty cycle correction circuit of a semiconductor memory apparatus includes a duty ratio correcting unit configured to correct a duty ratio of a clock signal according to levels of a first reference voltage and a second reference voltage, and to output the clock signal as a correction clock signal, a duty ratio detecting unit configured to count first and second counting signals in response to a duty ratio of the correction clock signal when a pump enable signal is enabled, a pump enable signal generating unit configured to generate the pump enable signal in response to the duty ratio of the correction clock signal, and a reference voltage generating unit configured to generate the first and second reference voltages in response to the first and second counting signals.