Invention Grant
- Patent Title: Amplification circuit, amplification circuit noise reducing method and program thereof
- Patent Title (中): 放大电路,放大电路降噪方法及程序
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Application No.: US12439971Application Date: 2007-09-13
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Publication No.: US07872524B2Publication Date: 2011-01-18
- Inventor: Haruya Ishizaki , Masayuki Mizuno
- Applicant: Haruya Ishizaki , Masayuki Mizuno
- Applicant Address: JP Tokyo
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JP Tokyo
- Priority: JP2006-250122 20060914
- International Application: PCT/JP2007/067792 WO 20070913
- International Announcement: WO2008/032763 WO 20080320
- Main IPC: H03F1/36
- IPC: H03F1/36

Abstract:
[Problems] to provide a CMOS low-noise amplification circuit which can reduce a chip area and design time, and which is easy to be digital-controlled from outside. [Means For Solving the Problems] The amplification circuit includes; an amplification stage (12) which amplifies an input signal up to an intended value; a sample and hold circuit (13) which samples the output signal from the amplification stage (12) by sampling the output signal with a sampling frequency which is at least twice the frequency band of the output signal to convert the output signal to a discrete time signal; a moving average calculation unit (15) which selects and outputs a particular frequency from the discrete time signal outputted from the sample and hold circuit (13) by a moving average operation; and a smoothing filter (17) which smoothes the output signal from the moving average calculation unit (15) and feed it back to the input of the amplification stage (12).
Public/Granted literature
- US20100045372A1 AMPLIFICATION CIRCUIT, AMPLIFICATION CIRCUIT NOISE REDUCING METHOD AND PROGRAM THEREOF Public/Granted day:2010-02-25
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