Invention Grant
- Patent Title: Scanning-line interpolating circuit, scanning-line interpolating method to be used in same circuit, and image display device provided with same circuit
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Application No.: US11510793Application Date: 2006-08-28
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Publication No.: US07872687B2Publication Date: 2011-01-18
- Inventor: Taketoshi Yamashita
- Applicant: Taketoshi Yamashita
- Applicant Address: JP Tokyo JP Kagoshima
- Assignee: Pioneer Corporation,Pioneer Plasma Display Corporation
- Current Assignee: Pioneer Corporation,Pioneer Plasma Display Corporation
- Current Assignee Address: JP Tokyo JP Kagoshima
- Agency: Sughrue Mion, PLLC
- Priority: JP2005-245978 20050826
- Main IPC: H04N7/01
- IPC: H04N7/01

Abstract:
A scanning-line interpolating circuit is provided which is capable of reducing jaggies on slanting lines and of keeping smoothness of interpolating signals achieved by using slanting lines having multiple angles for interpolation and of suppressing failures in displaying caused by erroneous judgement. When it is judged that there is matching in pixel data between three pixels or more on an upper line and three pixels or more on a lower line, an interpolating angle judging signal is corrected to be another interpolating angle judging signal corresponding to interpolation in up-and-down directions and isolated point is removed and another interpolating angle judging signal is output. Interpolating signals are blended with other interpolating signals corresponding to interpolation in same directions and at different angles and another interpolating signals are produced. One of second interpolating signals is selected based on the interpolating angle judging signal and an interpolating signal is produced.
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