Invention Grant
- Patent Title: In package ESD protections of IC using a thin film polymer
- Patent Title (中): 使用薄膜聚合物封装ESD保护IC
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Application No.: US12049726Application Date: 2008-03-17
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Publication No.: US07872841B2Publication Date: 2011-01-18
- Inventor: Yves Leduc , Nathalie Messina , Charvaka Duvvury , Kurt P. Wachtler
- Applicant: Yves Leduc , Nathalie Messina , Charvaka Duvvury , Kurt P. Wachtler
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Yingsheng Tung; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Priority: EP08100931 20080125
- Main IPC: H02H9/00
- IPC: H02H9/00

Abstract:
A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.
Public/Granted literature
- US20080278873A1 IN PACKAGE ESD PROTECTIONS OF IC USING A THIN FILM POLYMER Public/Granted day:2008-11-13
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