Invention Grant
US07872931B2 Integrated circuit with control circuit for performing retention test
有权
具有执行保持测试的控制电路的集成电路
- Patent Title: Integrated circuit with control circuit for performing retention test
- Patent Title (中): 具有执行保持测试的控制电路的集成电路
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Application No.: US12251010Application Date: 2008-10-14
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Publication No.: US07872931B2Publication Date: 2011-01-18
- Inventor: Khaled Fekih-Romdhane
- Applicant: Khaled Fekih-Romdhane
- Applicant Address: US NC Cary
- Assignee: Qimonda North America Corp.
- Current Assignee: Qimonda North America Corp.
- Current Assignee Address: US NC Cary
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C8/00 ; G11C29/00
Abstract:
An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal defines a retention period for the retention test.
Public/Granted literature
- US20100091595A1 INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST Public/Granted day:2010-04-15
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