A controller and a memory subsystem including a plurality of memory banks each having a plurality of memory devices, in which the controller includes a memory device configured to store an identification (ID) of each of the plurality of memory banks; and a control logic configured to read an ID of a memory bank to be accessed among the plurality of memory banks from the memory device, then output the ID, and then output a command. Each of the plurality of memory devices includes an input port, a register configured to store an ID of each memory device, and a determination circuit configured to receive and compare an ID input via the input port with the ID stored in the register and to generate a control signal according to a result of the comparison. The input port is enabled or disabled in response to the control signal.