Invention Grant
US07873887B2 Burn-in test circuit, burn-in test method, burn-in test apparatus, and a burn-in test pattern generation program product
失效
老化测试电路，老化测试方法，老化测试仪器和老化测试模式生成程序产品
- Patent Title: Burn-in test circuit, burn-in test method, burn-in test apparatus, and a burn-in test pattern generation program product
- Patent Title (中): 老化测试电路，老化测试方法，老化测试仪器和老化测试模式生成程序产品
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Application No.: US11619954Application Date: 2007-01-04
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Publication No.: US07873887B2Publication Date: 2011-01-18
- Inventor: Eiji Harada
- Applicant: Eiji Harada
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sughrue Mion, PLLC
- Priority: JP2006-000538 20060105
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
A burn-in test circuit according to the present invention includes a scan chain formed by a plurality of scan flip-flips connected in series, a circuit under test input with an output from one of the plurality of scan flip-flops as an activation signal, and a scan chain loop circuit being configured to an output signal of the scan chain determined according to an output of the circuit under test back to the scan chain.
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