Invention Grant
- Patent Title: Memory subsystems with fault isolation
- Patent Title (中): 内存子系统具有故障隔离
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Application No.: US12418581Application Date: 2009-04-04
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Publication No.: US07873895B2Publication Date: 2011-01-18
- Inventor: Michael Kennard Tayler
- Applicant: Michael Kennard Tayler
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
An exemplary memory subsystem with fault isolation comprises a first data bus routing data groupings in a lower 72 bits to a first memory expander, and a second data bus routing data groupings in an upper 72 bits to a second memory expander. A first memory module receives all of the data groupings in the lower 72 bits of each memory expander. A second memory module receives all of the data groupings in the upper 72 bits of each memory expander. A failure in any one or more bytes in an ECC word indicate failures in the computer memory system.
Public/Granted literature
- US20090193316A1 MEMORY SUBSYSTEMS WITH FAULT ISOLATION Public/Granted day:2009-07-30
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