Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch less than a threshold; determining a potential power gating cone (PGC) based on the identified low switching nodes; determining a power gating logic expression for the potential PGC that includes a minimum set of inputs to the potential PGC that are least switching; determining whether energy savings using the power gating logic expression meets a criteria; and accepting the potential PGC in response to meeting the criteria.