Invention Grant
- Patent Title: Method and apparatus for powering down analog integrated circuits
- Patent Title (中): 用于断电模拟集成电路的方法和装置
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Application No.: US11745778Application Date: 2007-05-08
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Publication No.: US07876146B2Publication Date: 2011-01-25
- Inventor: Guoqing Miao
- Applicant: Guoqing Miao
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM, Incorporated
- Current Assignee: QUALCOMM, Incorporated
- Current Assignee Address: US CA San Diego
- Agent William M. Hooks
- Main IPC: G05F1/10
- IPC: G05F1/10

Abstract:
A method and an apparatus powers down an analog integrated circuit. A power down circuit is electrically coupled to the analog circuit and is adapted to power down the analog circuit in response to receiving a power down signal. A node protection circuit is electrically coupled to the analog circuit and is adapted to provide a predetermined voltage potential to at least one predetermined node in the analog circuit in response to receiving the power down signal when a voltage potential at the at least one predetermined node is not determined by the power down circuit.
Public/Granted literature
- US20080278226A1 METHOD AND APPARATUS FOR POWERING DOWN ANALOG INTEGRATED CIRCUITS Public/Granted day:2008-11-13
Information query
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