Invention Grant
US07876861B2 Methods, apparatus, and systems for determining 1T state metric differences in an nT implementation of a viterbi decoder
有权
用于确定维特比解码器的nT实现中的1T状态量度差的方法,装置和系统
- Patent Title: Methods, apparatus, and systems for determining 1T state metric differences in an nT implementation of a viterbi decoder
- Patent Title (中): 用于确定维特比解码器的nT实现中的1T状态量度差的方法,装置和系统
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Application No.: US11696300Application Date: 2007-04-04
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Publication No.: US07876861B2Publication Date: 2011-01-25
- Inventor: Brian K. Gutcher , Kripa Venkatachalam
- Applicant: Brian K. Gutcher , Kripa Venkatachalam
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Duft Bornsen & Fishman, LLP
- Main IPC: H04L27/06
- IPC: H04L27/06

Abstract:
Methods, apparatus, and systems for generating bit-wise reliability information using a soft output Viterbi algorithm (“SOVA”) in an nT Viterbi decoder implementation devoid of 1T metric information. At each nT clock pulse 1T equivalent metric values are determined from the current nT metric information. 1T equivalent metric information is determined as values that sum to the corresponding nT metric information. Subtraction is then used to determine state metric difference information from the 1T equivalent metric values. The state metric difference information may then be used to estimate log likelihood ratio information for use in the SOVA algorithm to determine bit-wise reliability information.
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