A processor includes a first register, a control section and an arithmetical section. The processor has a first operation mode which allows the first area of a first register to be accessed and a second operation mode which allows a second area of the first register to be accessed. The first register includes the first area capable of holding data and the second area provided in the second operation mode and inhibited from holding data. The control section generates an address corresponding to the second area accessed in the second operation mode and is capable of reading data from an external memory device using the generated address. The arithmetical section, in the first operation mode, performs an arithmetical operation using the data held in the accessed first area and, in the second operation mode, performs an arithmetical operation using the data read at the control section.