Invention Grant
- Patent Title: Method of placing wires
- Patent Title (中): 布线方法
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Application No.: US12048791Application Date: 2008-03-14
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Publication No.: US07877709B2Publication Date: 2011-01-25
- Inventor: Daishin Itagaki
- Applicant: Daishin Itagaki
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sughrue Mion, PLLC
- Priority: JP2007-074082 20070322
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of placing wires for placing a shield wire with respect to a shield subject wire placed on a chip, a method includes setting a plurality of wire tracks on the chip, dividing the chip into at least a first area and a second area according to a division boundary, confirming whether the shield subject wire exists around the division boundary in the second area when the division boundary is not laid on top of the wire track, and determining whether to place the shield wire on a wire track being adjacent to division boundary in the first area based on the confirming.
Public/Granted literature
- US20080233732A1 METHOD OF PLACING WIRES Public/Granted day:2008-09-25
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