Invention Grant
- Patent Title: Secured verification of configuration data for field programmable gate array devices
- Patent Title (中): 安全验证现场可编程门阵列器件的配置数据
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Application No.: US10621873Application Date: 2003-07-16
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Publication No.: US07878902B2Publication Date: 2011-02-01
- Inventor: Harold E. Mattice , Richard Wilder , Chauncey W. Griswold
- Applicant: Harold E. Mattice , Richard Wilder , Chauncey W. Griswold
- Applicant Address: US NV Reno
- Assignee: IGT
- Current Assignee: IGT
- Current Assignee Address: US NV Reno
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: A63F9/24
- IPC: A63F9/24

Abstract:
A method and apparatus for providing automated and secured verification of configuration data for a volatile progrannmable electronic device, such as an FPGA, is disclosed. A configurator including at least one memory unit, such as a ROM or EEPROM, contains a configuration file, which file is transferred to the volatile programmable electronic device or FPGA on demand. Data from the configuration file is compared with data from a separate custodial file, which custodial file is substantially identical to the configuration file and resides in a location separate from the memory unit or units that store the actual configuration file. In some instances the comparison is made before any actual loading of the configuration file into the FPGA occurs, whereby loading is prohibited if no match is confirmed, while in other instances the FPGA is configured using the configuration file and is then shut down if no match is later confirmed.
Public/Granted literature
- US20050014559A1 Secured verification of configuration data for field programmable gate array devices Public/Granted day:2005-01-20
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