Invention Grant
- Patent Title: Manufacturing method of semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件的制造方法
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Application No.: US12101956Application Date: 2008-04-11
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Publication No.: US07879516B2Publication Date: 2011-02-01
- Inventor: Toshihide Kawachi , Hidekimi Fudo
- Applicant: Toshihide Kawachi , Hidekimi Fudo
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Miles & Stockbridge P.C.
- Priority: JP2007-136071 20070523
- Main IPC: G03C5/00
- IPC: G03C5/00 ; G03F7/00

Abstract:
In the semiconductor integrated circuit device lithography process it is becoming more and more essential to control both exposure dose and focus value independently with a high accuracy. Using a wafer treated precedingly, a section profile of a photoresist is acquired by the technique of scatterometry, then both exposure dose and focus value are estimated independently with a high accuracy on the basis of the section profile thus acquired and using a conjectural expression obtained by the technique of multivariate analysis, and a focus setting in the exposure of a succeedingly treated wafer is corrected on the basis of the estimated exposure dose and focus value.
Public/Granted literature
- US20080292977A1 MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2008-11-27
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