Invention Grant
US07879702B2 Method for manufacturing a semiconductor device including a memory cell array area and peripheral circuit area
有权
用于制造包括存储单元阵列区域和外围电路区域的半导体器件的方法
- Patent Title: Method for manufacturing a semiconductor device including a memory cell array area and peripheral circuit area
- Patent Title (中): 用于制造包括存储单元阵列区域和外围电路区域的半导体器件的方法
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Application No.: US11773666Application Date: 2007-07-05
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Publication No.: US07879702B2Publication Date: 2011-02-01
- Inventor: Yoshihiro Takaishi
- Applicant: Yoshihiro Takaishi
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Whitham Curtis Christofferson & Cook, PC
- Priority: JP2006-187779 20060707
- Main IPC: H01L21/425
- IPC: H01L21/425
Abstract:
A method for manufacturing a semiconductor device includes the consecutive steps of selectively implanting first-conductivity-type impurities into a silicon substrate in a memory cell array area to form first source/drain regions, heat treating to diffuse the impurities in the first source/din regions; selectively implanting impurities into the silicon substrate in a peripheral circuit area to form second source/drain regions in the peripheral circuit area.
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