Invention Grant
- Patent Title: Local interconnect having increased misalignment tolerance
- Patent Title (中): 本地互连具有增加的不对准公差
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Application No.: US11616544Application Date: 2006-12-27
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Publication No.: US07879718B2Publication Date: 2011-02-01
- Inventor: Simon S. Chan
- Applicant: Simon S. Chan
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Agency: Harrity & Harrity, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.
Public/Granted literature
- US20080157160A1 LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE Public/Granted day:2008-07-03
Information query
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