Invention Grant
- Patent Title: Interconnect structure and method of manufacturing the same
- Patent Title (中): 互连结构及其制造方法
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Application No.: US12334505Application Date: 2008-12-14
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Publication No.: US07879719B2Publication Date: 2011-02-01
- Inventor: Eun-Soo Jeong
- Applicant: Eun-Soo Jeong
- Applicant Address: KR Seoul
- Assignee: Dongbu HiTek Co., Ltd.
- Current Assignee: Dongbu HiTek Co., Ltd.
- Current Assignee Address: KR Seoul
- Agency: Sherr & Vaughn, PLLC
- Priority: KR10-2007-0136244 20071224
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A semiconductor device and a method for manufacturing the device that minimizes a line width while maximizing integration density of the semiconductor device. The method includes forming an interlayer insulating film on a semiconductor substrate, and then forming a first via hole in the interlayer insulating film, and then forming a resin material in the first via hole, and then forming a plurality of second via holes in the interlayer insulating film laterally, and then forming a resin material in the second via holes, and then simultaneously forming a plurality of third via holes in the interlayer insulating film and a trench spatially above and corresponding to the first via hole, and then removing the resin formed in the first via hole and the second via holes, and then simultaneously forming metal layers in the first via hole and the second and third via holes and the trench.
Public/Granted literature
- US20090160064A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE Public/Granted day:2009-06-25
Information query
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