Invention Grant
US07879723B2 Semiconductor device manufacturing method, wiring and semiconductor device
有权
半导体器件制造方法，布线和半导体器件
- Patent Title: Semiconductor device manufacturing method, wiring and semiconductor device
- Patent Title (中): 半导体器件制造方法，布线和半导体器件
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Application No.: US12320655Application Date: 2009-01-30
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Publication No.: US07879723B2Publication Date: 2011-02-01
- Inventor: Kyoichi Suguro , Mitsuaki Izuha
- Applicant: Kyoichi Suguro , Mitsuaki Izuha
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2004-381419 20041228
- Main IPC: H01L21/321
- IPC: H01L21/321 ; H01L21/3213 ; H01L21/4763
Abstract:
In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.
Public/Granted literature
- US20090203181A1 Semiconductor device manufacturing method, wiring and semiconductor device Public/Granted day:2009-08-13
Information query
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