A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers the entire surface of the substrate. A drain leader line (104) made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line (107) is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (105). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.