Invention Grant
- Patent Title: Semiconductor device with passivation layer covering wiring layer
- Patent Title (中): 具有钝化层的半导体器件覆盖了布线层
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Application No.: US11386106Application Date: 2006-03-22
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Publication No.: US07880256B2Publication Date: 2011-02-01
- Inventor: Nobuyuki Takai , Takuya Suzuki , Yuji Tsukada
- Applicant: Nobuyuki Takai , Takuya Suzuki , Yuji Tsukada
- Applicant Address: JP Moriguchi-shi
- Assignee: Sanyo Electric Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.
- Current Assignee Address: JP Moriguchi-shi
- Agency: Morrison & Foerster LLP
- Priority: JP2005-087685 20050325; JP2006-045448 20060222
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L21/4763 ; H01L21/70

Abstract:
The invention provides a semiconductor device with a bonding pad made of a wiring layer including aluminum and its manufacturing method that enhance the yield of the semiconductor device. The method of manufacturing the semiconductor device of the invention includes removing a portion of an antireflection layer (e.g. made of a titanium alloy) formed on an uppermost second wiring layer (e.g. made of aluminum) on a semiconductor substrate by etching, forming a passivation layer covering the antireflection layer and a portion of the second wiring layer where the antireflection layer is not formed and having an opening exposing the other portion of the second wiring layer, and dividing the semiconductor substrate into a plurality of semiconductor dice by dicing. These processes can prevent the antireflection layer from being exposed in the opening, and this can prevent a component of the second wiring layer from being eluted due to cell reaction between the second wiring layer and the antireflection layer as has been seen in the conventional art.
Public/Granted literature
- US20060249845A1 Semiconductor device and manufacturing method of the same Public/Granted day:2006-11-09
Information query
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