Invention Grant
- Patent Title: Isolation technique allowing both very high and low voltage circuits to be fabricated on the same chip
- Patent Title (中): 隔离技术允许在同一芯片上制造非常高和低电压电路
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Application No.: US12165933Application Date: 2008-07-01
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Publication No.: US07880261B2Publication Date: 2011-02-01
- Inventor: Peter J. Hopper , William French , Ann Gabrys
- Applicant: Peter J. Hopper , William French , Ann Gabrys
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Dergosits & Noah LLP
- Main IPC: H01L21/70
- IPC: H01L21/70
Abstract:
An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk.
Public/Granted literature
- US20100001365A1 ISOLATION TECHNIQUE ALLOWING BOTH VERY HIGH AND LOW VOLTAGE CIRCUITS TO BE FABRICATED ON THE SAME CHIP Public/Granted day:2010-01-07
Information query
IPC分类:
