Invention Grant
- Patent Title: Semiconductor device
- Patent Title (中): 半导体器件
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Application No.: US12360357Application Date: 2009-01-27
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Publication No.: US07880262B2Publication Date: 2011-02-01
- Inventor: Fumitoshi Yamamoto
- Applicant: Fumitoshi Yamamoto
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: McDermott Will & Emery LLP
- Priority: JP2008-016656 20080128
- Main IPC: H01L21/70
- IPC: H01L21/70

Abstract:
An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through the n− epitaxial layer to reach the p-type impurity region. Therefore, a semiconductor device is obtained which allows the chip size to be reduced easily and is highly effective in preventing movement of electrons from the output transistor formation region to the other element formation region.
Public/Granted literature
- US20090189247A1 SEMICONDUCTOR DEVICE Public/Granted day:2009-07-30
Information query
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