Invention Grant
- Patent Title: Post passivation interconnection schemes on top of the IC chips
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Application No.: US12370617Application Date: 2009-02-13
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Publication No.: US07880304B2Publication Date: 2011-02-01
- Inventor: Mou-Shiung Lin , Chiu-Ming Chou , Chien-Kang Chou
- Applicant: Mou-Shiung Lin , Chiu-Ming Chou , Chien-Kang Chou
- Applicant Address: TW Hsinchu
- Assignee: Megica Corporation
- Current Assignee: Megica Corporation
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L23/522
- IPC: H01L23/522

Abstract:
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
Public/Granted literature
- US20090146305A1 POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS Public/Granted day:2009-06-11
Information query
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