Invention Grant
- Patent Title: Stacked semiconductor package and method for manufacturing the same
- Patent Title (中): 堆叠半导体封装及其制造方法
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Application No.: US11953134Application Date: 2007-12-10
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Publication No.: US07880311B2Publication Date: 2011-02-01
- Inventor: Kwon Whan Han
- Applicant: Kwon Whan Han
- Applicant Address: KR Kyoungki-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Kyoungki-do
- Agency: Ladas & Parry LLP
- Priority: KR10-2007-0109766 20071030
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips, each semiconductor chip having a first face, a second face opposite to the first face, and a circuit part. A thorough portion passes through the first and second faces of the semiconductor chip. A recess part is formed in a portion of the second face where the second face and the through portion meets. A through electrode is electrically connected to the circuit part and is disposed inside of the through portion. A connection member is disposed in the recess part to electrically connect the through electrodes of adjacent stacked semiconductor chips. And the semiconductor chip module is mounted to a substrate. The stacked semiconductor package prevents both gaps between semiconductor chips and misalignment of the through electrode.
Public/Granted literature
- US20090108468A1 STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2009-04-30
Information query
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