Invention Grant
- Patent Title: Multilayer semiconductor device
- Patent Title (中): 多层半导体器件
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Application No.: US12264301Application Date: 2008-11-04
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Publication No.: US07880491B2Publication Date: 2011-02-01
- Inventor: Yukitoshi Hirose
- Applicant: Yukitoshi Hirose
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2004-306357 20041021
- Main IPC: G01R31/26
- IPC: G01R31/26
Abstract:
The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips includes a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device also includes a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation.
Public/Granted literature
- US20090065774A1 MULTILAYER SEMICONDUCTOR DEVICE Public/Granted day:2009-03-12
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