A logic circuit with a simple configuration and good current efficiency is provided. The logic circuit includes a two-terminal bistable switching element (1) having characteristics which maintain states, a first switching element (25) one end of which is connected to one terminal of the two-terminal bistable switching element (1), a second switching element (29) one end of which is connected to the other terminal of the two-terminal bistable switching element (1) via a resistance element (27), and first and second pulse input terminals (33, 37) respectively connected to the one terminal and the other terminal of the two-terminal bistable switching element (1). A bias voltage is applied across the other end of the first switching element (25) and the other end of the second switching element (27), and a trigger pulse is input from the first and second pulse input terminals (33, 37).