Invention Grant
- Patent Title: Logic stages with inversion timing control
- Patent Title (中): 具有反转定时控制的逻辑级
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Application No.: US12563389Application Date: 2009-09-21
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Publication No.: US07880504B2Publication Date: 2011-02-01
- Inventor: Hitoshi Iwai
- Applicant: Hitoshi Iwai
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2009-060890 20090313
- Main IPC: H03K19/096
- IPC: H03K19/096 ; H03K17/28

Abstract:
A semiconductor integrated circuit includes logic circuits connected in a plurality of stages, a voltage-level inverting unit that is inserted in a signal transmission path of the logic circuits and inverts a voltage level input to the logic circuits, and an inversion-timing control unit that controls inversion timing for the voltage level inverted by the voltage-level inverting unit.
Public/Granted literature
- US20100231258A1 SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2010-09-16
Information query
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