Invention Grant
- Patent Title: Resolving metastability
- Patent Title (中): 解决亚稳态
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Application No.: US12713412Application Date: 2010-02-26
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Publication No.: US07880506B2Publication Date: 2011-02-01
- Inventor: Stephen Felix
- Applicant: Stephen Felix
- Applicant Address: US DE Wilmington
- Assignee: Icera Inc.
- Current Assignee: Icera Inc.
- Current Assignee Address: US DE Wilmington
- Priority: GB0903687.2 20090303
- Main IPC: H03K19/00
- IPC: H03K19/00

Abstract:
A logic circuit latch including an input stage for receiving a logical input signal and a pair of differential amplifiers, each having an input operatively coupled to the input stage, and at least one of them having an output arranged to supply the logical output of the latch. Each of the differential amplifiers includes a transistor connected as a load, and an output of each of the differential amplifiers is coupled to bias the load transistor of the other differential amplifier. If the latch switches from the transparent state to the closed state while the logical input signal is transitioning between logical levels, the differential amplifiers drive up the logical output of the latch if the logical input signal transitions from a first to a second logical level, and drive down the logical output of the latch if the input signal transitions from the second to the first logical level.
Public/Granted literature
- US20100225351A1 Resolving Mestastability Public/Granted day:2010-09-09
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