The differential drive circuit generates a differential drive signal having a root mean square value defined by a digital input value. The differential drive signal includes a first differential component and a second differential component. The circuit comprises a first differential component generator and a second differential component generator. The first differential component generator is for counting the clock signal to generate successive values of a periodic count. Each of the values includes a most-significant bit. The first differential component generator is additionally for generating the first differential component in response to successive ones of the most-significant bit of the count. The second differential component generator is for generating the second differential component in response to the digital input value and the successive values of the count.