A test mode signal generator for a semiconductor memory device includes a test mode entry control unit that receives test entry mode setting addresses inputted in response to a test mode register set signal. The test mode entry control unit outputs a plurality of test entry mode signals and a test mode set signal according to the test entry mode setting addresses. A latch unit latches test address decoding signals in response to the test mode set signal, and outputs test mode signals by allowing the latched test address decoding signals to be controlled by the respective test entry mode signals. A test mode signal is generated for each test entry mode, so that the number of test modes is increased without increasing the number of addresses for supporting test modes.